1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly relates to a semiconductor memory device having cell capacitors and a manufacturing method of the semiconductor memory device.
2. Description of Related Art
Generally, in a DRAM (Dynamic Random Access Memory), a cell transistor and a cell capacitor that constitute one memory cell are stacked in a perpendicular direction (a normal direction of a semiconductor substrate). The reason for adopting such a stacked structure is to reduce the total area of a memory cell area. Meanwhile, in such a stacked structure, an area allocatable to one cell capacitor (an area of a cell capacitor in a direction parallel to a surface of a semiconductor substrate, hereinafter, “allocatable area”) is restricted to an area equal to or smaller than that of one cell transistor (hereinafter, “cell area”). Therefore, the allocatable area decreases year after year under the circumstances that the cell area decreases year after year following the development of downsizing technologies. Accordingly, when the stacked structure is adopted, it is necessary to take various measures to secure a necessary capacity of the cell capacitor.
In an example of these measures, a facing direction in which an upper electrode faces a lower electrode is set to a horizontal direction (a direction parallel to a surface of a substrate). A cell capacitor in this example (hereinafter, “vertical capacitor”) has a property of having a larger electrode area as the height of the vertical capacitor becomes larger. Therefore, it is possible to secure a necessary capacity by increasing the height of the vertical capacitor even in the case that the cell area is small. Examples of such a vertical capacitor are disclosed in Japanese Patent Application Laid-open Nos. 2006-216649, 2009-076639, and H09-266292.
However, the vertical capacitor has a problem that a processing margin becomes smaller as the height of the vertical capacitor is larger. Therefore, while the vertical capacitor is helpful from a viewpoint of securing a minimum capacity necessary to operate functions of a DRAM, it is inaptitude to allow the capacity to have a leeway. That is, it is effective for the DRAM to give a sufficient margin to the capacity of the cell capacitor from a viewpoint of the improvement in refresh characteristics. But it is difficult for the capacity of the vertical capacitor to have such a margin from a viewpoint of ensuring a yield ratio.
Furthermore, it is generally necessary to configure a capacitor such that the thicknesses of upper and lower electrodes are equal to or larger than a certain value in a direction perpendicular to a facing direction in which the upper electrode faces the lower electrode. In the vertical capacitor, the thicknesses of these electrodes are those in a horizontal direction. However, the thicknesses in the horizontal direction are restricted by the cell area. As a result, along with the further development in the downsizing of cell transistors, it becomes difficult to ensure that the thicknesses are equal to or larger than the certain value, and therefore it is predicted that adopting vertical capacitors becomes difficult in the first place.